`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   00:25:25 11/22/2014
// Design Name:   RxConFifo
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/Xilin/uart-arquitectura-2014/RxConFifoTest.v
// Project Name:  UART
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RxConFifo
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RxConFifoTest;

	// Inputs
	reg clk;
	reg reset;
	reg rx;
	reg leer;

	// Outputs
	wire tx;
	wire llena;
	wire vacia;
	wire [7:0] salida;

	// Instantiate the Unit Under Test (UUT)
	RxConFifo uut (
		.clk(clk), 
		.reset(reset), 
		.rx(rx), 
		.leer(leer), 
		.tx(tx), 
		.llena(llena), 
		.vacia(vacia), 
		.salida(salida)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		rx = 1;
		leer = 0;

		// Wait 100 ns for global reset to finish
		#100;
      reset = 0;  
		// Add stimulus here
		#10400
		rx = 0; //Bit de start para 00001111
		#10400
		rx = 1;
		#10400
		rx = 1;
		#10400
		rx = 1;
		#10400
		rx = 1;
		#10400
		rx = 0;
		#10400
		rx = 0;
		#10400
		rx = 0;
		#10400
		rx = 0;
		#10400
		rx = 1; // bit de fin
		#10400;
		//Borramos
		leer = 1;
		#100;
		leer = 0;
		#100;
		rx = 0; //Bit de start para 01010101
		#10400
		rx = 1;
		#10400
		rx = 0;
		#10400
		rx = 1;
		#10400
		rx = 0;
		#10400
		rx = 1;
		#10400
		rx = 0;
		#10400
		rx = 1;
		#10400
		rx = 0;
		#10400
		rx = 1; // bit de fin
		#10400;
		leer = 1;
		#100;
		leer = 0;
		#100;
	end
	
 always begin
#1; clk = ~clk; 
end
endmodule

